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asahi kasei [ak4665a] ms0440-e-01 2006/05 - 1 - - general description the ak4665a is a 20bit codec with built-in input pga and headphone amplifier. the ak4665a includes a microphone/line input selector and an alc circuit for input, and a stereo line output buffer, analog volume controls and capless stereo headphone amplifier for output. the ak4665a also features an analog mixing circuit that allows easy interfacing in mobile phone and portable communication designs. the integrated headphone amplifier features ?pop-free? power-on/off, a mute control and delivers 31mw of power into 16 ? load. the ak4665a is housed in a 32pin qfn package, making it suitable for portable applications. feature ? 2ch 20bit adc - mono mic-amp: +30db/+6db/0db/ ? 6db - single-ended input - input selector - digital alc: +41.25db ? 54db, 0.375db step, mute - digital hpf for dc-offset cancellation - i/f format: 20bit msb justified, i 2 s - s/n: 93db ? 2ch 20bit dac - digital att: 0db ? 127db, mute, 0.5db step (soft transition) - soft mute - digital de-emphasis filter: 32khz, 44.1khz and 48khz - bass boost - i/f format: i 2 s, 20bit msb justified, 20bit/16bit lsb justified ? sampling rate: 8khz 48khz ? system clock: 256fs/512fs ? analog mixing circuit ? stereo lineout - alc: +19.5db ? 12db, 0.5db step - analog volume: 0db ? 30db, mute, 2db step ? capless stereo headphone amplifier - output power: 31mw x 2ch @16 ? - line output mode: 1vrms @10k ? - charge pump circuit for negative power supply - s/n: 88db ? p interface: 3-wire ? power management ? power supply: - avdd, dvdd, hvdd: 2.6v 3.6v - tvdd (digital i/o): 1.6v 3.6v ? power supply current: 20ma ? ta: ? 30 85 c ? small package: 32pin qfn (5mm x 5mm, 0.5mm pitch) 20-bit stereo codec with mic/hp- a mp ak4665 a
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 2 - adc audio i/f controller hp-amp hpl da c hpr lout control register dv dd pmhpl pmadc pm lo pmdac sdto lrck bick sdti mclk cs n cclk cdt i pdn datt smute vcom vcom av dd vref vref pmmp mic-amp micin mic power mpwr hv dd hv ss cn nv ss cp charge pu mp a inr1 a inl1 ro ut tv dd att hpf alc1 alc2 av ss dv ss pmcp dem boost pmvcm lin rin min lpf lpf lpf pmhpl or pmhpr or pmlo pmhpr figure 1. block diagram
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 3 - ? ordering guide AK4665AEN ? 30 +85 c 32pin qfn (0.5mm pitch) akd4665a evaluation board for ak4665a ? pin layout a vss a vdd vcom vref pdn csn cclk cdti micin mpwr a inl1 a inr1 lin rin min lout lrck mclk bick sdti sdto tvdd dvss dvdd rout hpr hpl nvss hvss hvdd cn cp a k4665aen top view 25 26 27 28 29 30 31 32 24 23 22 1 16 15 14 13 12 11 10 9 21 20 19 18 17 2 3 4 5 6 7 8 ? comparison table between ak4569 and ak4665a function ak4569 ak4665a hp-amp power supply single power supply dual power supply (single power supply as external case) hp-amp output 8.7mw@16 ? 31mw@16 ? mic-amp no yes mic-power no yes alc for recording analog mic: +32 ? 19db, 0.5db step line: +20 ? 31db, 0.5db step digital +41.25 ? 54db, 0.375db step alc for playback no yes loopback no yes sdto disable no yes lineout mono stereo mclk cmos or ac coupling input cmos input power supply 2.5 3.6v avdd, dvdd, hvdd: 2.6 3.6v tvdd: 1.6 3.6v package 28qfn (5.2mm x 5.2mm, 0.5mm pitch) 32qfn (5mm x 5mm, 0.5mm pitch)
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 4 - pin/function no. pin name i/o function 1 lrck i l/r clock pin this clock determines which audio channel is currently being output on sdto pin and input on sdti pin. 2 mclk i master clock input pin 3 bick i serial bit clock pin this clock is used to latch audio data. 4 sdti i audio data input pin 5 sdto o audio data output pin sdto pin goes to dvss when pdn pin is ?l? or pmadc bit is ?0?. 6 tvdd - digital i/o power supply pin 7 dvss - digital ground pin 8 dvdd - digital power supply pin 9 cp o positive charge pump capacitor terminal pin 10 cn i negative charge pump capacitor terminal pin 11 hvdd - power supply pin for headphone amplifier and charge pump circuit 12 hvss - ground pin for headphone amplifier and charge pump circuit 13 nvss o negative voltage output pin for headphone amplifier and charge pump circuit 14 hpl o lch headphone amplifier output pin hpl pin goes to avss when pmhpl bit is ?0?. 15 hpr o rch headphone amplifier output pin hpr pin goes to avss when pmhpr bit is ?0?. 16 rout o rch analog output pin 17 lout o lch analog output pin 18 min i mono analog input pin 19 rin i rch analog input pin 20 lin i lch analog input pin 21 ainr1 i rch analog input 1 pin for adc (line input) 22 ainl1 i lch analog input 1 pin for adc (line input) 23 mpwr o mic power supply pin 24 micin i mic input pin 25 avss - analog ground pin 26 avdd - analog power supply pin 27 vcom o common voltage output pin, 1.2v (typ, respect to avss) normally connected to avss pin with a 0.1 f ceramic capacitor in parallel with a 2.2 f electrolytic capacitor. vcom pin goes to avss when pmvcm bit = ?0?. 28 vref o reference voltage output pin, 2.1v (typ, respect to avss) reference voltage output pin, 2.1v (typ, respect to avss) normally connected to avss pin with a 0.1 f ceramic capacitor in parallel with a 4.7 f electrolytic capacitor. vref pin goes to avss when pmvcm bit = ?0?. 29 pdn i power-down pin when ?l?, the ak4665a is in power-down mode and is held in reset. the ak4665a should always be reset upon power-up. 30 csn i control data chip select pin 31 cclk i control clock input pin 32 cdti i control data input pin note 1. do not allow digital input pins except analog input pins (micin, ainl1, ainr1, lin, rin and min pins) to float.
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 5 - ? handling of unused pin the unused i/o pins should be processed appropriately as below. classification pin name setting analog hpr, hpl, lout, rout, micin, ainr1, ainl1, mpwr these pins should be open. sdto this pin should be open. digital sdti this pin should be connected to dvss. absolute maximum rating (avss, dvss, hvss=0v; note 2) parameter symbol min max units power supplies analog avdd ? 0.3 4.0 v digital dvdd ? 0.3 4.0 v digital i/o tvdd ? 0.3 4.0 v hp-amp hvdd ? 0.3 4.0 v |avss ? hvss| (note 3) ? gnd1 - 0.3 v |avss ? dvss| (note 3) ? gnd2 - 0.3 v input current (any pins except for supplies) iin - 10 ma analog input voltage (note 4) vina ? 0.3 (avdd+0.3) or 4.0 v digital input voltage (note 5) vind ? 0.3 (tvdd+0.3) or 4.0 v ambient temperature ta ? 30 85 c storage temperature tstg ? 65 150 c note 2. all voltages with respect to ground note 3. avss, dvss and hvss must be connected to the same analog ground plane. note 4. min, rin, lin, micin, ainr1, ainl1 pins max is smaller value between (avdd+0.3)v and 4.0v. note 5. pdn, csn, cclk, cdti , lrck, mclk, bick, sdti pins max is smaller value between (tvdd+0.3)v and 4.0v. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommend operating conditions (avss, dvss, hvss=0v; note 2) parameter symbol min typ max units power supplies analog avdd 2.6 3.0 3.6 v digital dvdd 2.6 3.0 3.6 v hp-amp hvdd 2.6 3.0 3.6 v digital i/o tvdd 1.6 3.0 dvdd v difference avdd ? dvdd ? 0.3 0 +0.3 v note 2. all voltages with respect to ground note 6. if each power supply is gradually switched on or off, some supply current may occur at the other power supply that is still switched on during the supply voltage transition time. note: akm assumes no responsibi lity for usage beyond the condi tions in this datasheet.
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 6 - analog characteristics (ta=25 c; avdd=dvdd=hvdd=tvdd=3.0v, avss=dvss=hvss=0v; fs=44.1khz; alc1=dem =boost=alc2=off; attl=attr=atts= 0db; signal frequency =1khz; measurement band width=20hz 20khz; unless otherwise specified) parameter min typ max units adc resolution - - 20 bit mic amplifier: micin pin mgain1-0 bits = ?00? or ?01? 40 60 80 k ? input resistance mgain1-0 bits = ?10? or ?11? 20 30 40 k ? mgain1-0 bits = ?00? - 1.5 - vpp mgain1-0 bits = ?01? - 3.0 - vpp mgain1-0 bits = ?10? - 0.75 - vpp input voltage mgain1-0 bits = ?11? - 0.047 - vpp mgain1-0 bits = ?00? - 0 - db mgain1-0 bits = ?01? - ? 6 - db mgain1-0 bits = ?10? - +6 - db gain mgain1-0 bits = ?11? - +30 - db mic power supply: mpwr pin output voltage 1.8 2.0 2.2 v load resistance 2 - - k ? load capacitance - - 30 pf adc analog input characteristics: ainl1/ainr1 pins adc ivol, ivol=0db, alc1=off s/(n+d) ( ? 1dbfs) 78 90 - db d-range ( ? 60dbfs, a-weighted) 84 94 - db s/n (a-weighted) 84 94 - db interchannel isolation 80 100 - db interchannel gain mismatch - 0.2 0.5 db gain drift - 200 - ppm/ c input voltage 1.35 1.5 1.65 vpp input resistance 40 60 80 k ? power supply rejection (note 7) - 50 - db dac resolution 20 bit headphone-amp: (hpl/hpr pins) (note 8) r l =16 ? , hpg bit = ?0? 0dbfs output, hpg bit = ?0?, po=17mw@16 ? 40 60 - db ? 3dbfs output, hpg bit = ?1?, po=31mw@16 ? - 20 - db s/(n+d) 0dbfs output, hpg bit = ?1?, r l =10k ? - 80 - db d-range ( ? 60dbfs output, a-weighted) 80 88 - db s/n (a-weighted) 80 88 - db interchannel isolation 60 80 - db interchannel gain mismatch - 0.2 1.0 db gain drift - 200 - ppm/ c 0dbfs output, hpg bit = ?0?, r l =16 ? 1.35 1.5 1.65 vpp ? 3dbfs output, hpg bit = ?1?, r l =16 ? - 2.0 - vpp output voltage 0dbfs output, hpg bit = ?1?, r l =10k ? - 2.83 - vpp load resistance 16 - - ? load capacitance - - 300 pf power supply rejection (note 7) - 50 - db note 7. psr is applied to avdd, dvdd and hvdd with 1khz, 50mvpp. note 8. dachl=dachr bits = ?1?, minhl=minhr=li nhl=rinhr bits = ?0?, attl7-0=attr7-0 bits=0db.
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 7 - parameter min typ max units stereo line output: (lout/rout pins) (note 9) s/(n+d) (0dbfs output) 72 84 - db s/n (a-weighted) 80 88 - db interchannel isolation 70 90 - db interchannel gain mismatch - 0.2 0.5 db gain drift - 200 - ppm/ c output voltage 1.35 1.5 1.65 vpp load resistance (note 10) 10 - - k ? load capacitance - - 30 pf power supply rejection (note 7) - 50 - db output volume (opga): (lout/rout pins) step size 1 2 3 db gain control range ? 30 0 db analog input: (lin/rin/min pins) input resistance 100 200 300 k ? gain lin hpl, rin hpr, hpg bit = ?0?, ling bit = ?0? ? 1 0 +1 db lin hpl, rin hpr, hpg bit = ?0?, ling bit = ?1? - ? 12 - db lin hpl, rin hpr, hpg bit = ?1?, ling bit = ?0? - +5.5 - db lin hpl, rin hpr, hpg bit = ?1?, ling bit = ?1? - ? 6.5 - db min hpl/hpr, hpg bit = ?0? ? 1 0 +1 db min hpl/hpr, hpg bit = ?1? - +5.5 - db lin/min lout, rin/min rout, atts=0db ? 1 0 +1 db power supplies power supply current: avdd+dvdd+tvdd+hvdd normal operation (pdn pin = ?h?) (note 11) - 20 30 ma power-down mode (pdn pin = ?l?) (note 12) - 1 100 a note 9. dacl=dacr bits = ?1?, li nl=rinr=minl=minr bits = ?0?, attl7-0=attr7-0=atts3-0 bits=0db. note 10. ac load note 11. all blocks are powered-up (mvcm=pmadc=pmdac=pmhpl=pmhpr=pmlo=pmcp=pmmp bits = ?1?), and hp-amp output is off. output current of mpwr pin is 0ma. avdd=12ma(typ), dvdd+tvdd=2ma(typ), hvdd=6ma(typ). 14ma(typ) at playback only (pmvcm=pmdac=pmhpl=pmhpr=pmlo=pmcp bits = ?1?, pmadc bit = ?0?), avdd=6.5ma(typ), dvdd+tvdd=1.5ma(typ), hvdd=6ma(typ). note 12. all digital input pins including clock pins (mclk, bick and lrck) are held at dvdd or dvss. pdn pin is held at dvss.
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 8 - filter characteristics (ta=25 c; avdd, dvdd, hvdd=2.6 3.6v; tvdd=1.6 3.6v; fs=44.1khz; dem=off; boost=off) parameter symbol min typ max units adc digital filter (lpf): passband (note 13) 0.16db pb 0 - 17.3 khz ? 0.66db - 19.4 - khz ? 1.1db - 19.9 - khz ? 6.9db - 22.1 - khz stopband (note 13) sb 26.1 - - khz passband ripple pr - - 0.1 db stopband attenuation sa 73 - - db group delay (note 14) gd - 17 - 1/fs group delay distortion ? gd - 0 - s adc digital filter (hpf): frequency response (note 13) ? 3db fr - 3.4 - hz ? 0.5db - 10 - hz ? 0.1db - 22 - hz dac digital filter: (note 15) passband (note 13) 0.1db pb 0 - 19.6 khz ? 0.7db - 20.0 - khz ? 6.0db - 22.05 - khz stopband (note 13) sb 25.2 - - khz passband ripple pr - - 0.01 db stopband attenuation sa 59 - - db group delay (note 14) gd - 17.5 - 1/fs group delay distortion ? gd - 0 - s dac digital filter + analog filter: (note 15) frequency response: 0 20.0khz fr - 1.0 - db analog filter: (note 16) frequency response: 0 20.0khz fr - 1.0 - db boost filter: (note 17) frequency response 20hz fr - 5.76 - db min 100hz - 2.92 - db 1khz - 0.02 - db 20hz fr - 10.80 - db mid 100hz - 6.84 - db 1khz - 0.13 - db 20hz fr - 16.06 - db max 100hz - 10.54 - db 1khz - 0.37 - db note 13. the passband and stopband frequencies scale with fs. for example (dac), pb=0.44*fs(@ 0.1db), sb=0.57*fs(@ ? 59db). note 14. this is the calculated delay time caused by digital filtering. this time is measured from the input of analog signal to setting the 20 bit data of both channels on input regist er to the output register of adc. for dac, this time is from setting the 20 bit data of both channels on input register to the output of analog signal. note 15. boost off (bst1-0 bits = ?00?) note 16. lin hpl, rin hpr, min hpl/hpr. note 17. these frequency responses scal e with fs. if high-level signal is input, the ak4665a clips at low frequency.
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 9 - dc characteristics (ta=25 c; avdd, dvdd, hvdd = 2.6 3.6v; tvdd=1.6 3.6v) parameter symbol min typ max units high-level input voltage 2.2v tvdd 3.6v vih 70 % tvdd - - v 1.6v tvdd<2.2v vih 80 % tvdd - - v low-level input voltage 2.2v tvdd 3.6v vil - - 30 % tvdd v 1.6v tvdd<2.2v vil - - 20 % tvdd v high-level output voltage (iout= ? 100 a) voh tvdd ? 0.4 - - v low-level output voltage (iout= 100 a) vol - - 0.4 v input leakage current iin - - 10 a
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 10 - switching characteristics (ta=25 c; avdd, dvdd, hvdd = 2.6 3.6v; tvdd=1.6 3.6v; c l = 20pf) parameter symbol min typ max units master clock timing frequency fclk 2.048 - 24.576 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns lrck timing frequency fs 8 44.1 48 khz duty cycle duty 45 55 % serial interface timing (note 18) bick period tbck 325.5 - - ns bick pulse width low tbckl 130 - - ns pulse width high tbckh 130 - - ns lrck edge to bick ? ? (note 19) tlrb 50 - - ns bick ? ? to lrck edge (note 19) tblr 50 - - ns lrck to sdto(msb) tlrs - - 80 ns bick ? ? to sdto tbsd - - 80 ns sdti hold time tsdh 50 - - ns sdti setup time tsds 50 - - ns control interface timing cclk period tcck 200 - - ns cclk pulse width low tcckl 80 - - ns pulse width high tcckh 80 - - ns cdti setup time tcds 40 - - ns cdti hold time tcdh 40 - - ns csn ?h? time tcsw 150 - - ns csn ? ? to cclk ? ? tcss 50 - - ns cclk ? ? to csn ? ? tcsh 50 - - ns power-down & reset timing pdn pulse width (note 20) tpd 150 - - ns pmadc ? ? to sdto valid (note 21) tpdv - 2081 - 1/fs note 18. refer to ?serial data interface?. note 19. bick rising edge must not occur at the same time as lrck edge. note 20. the ak4665a can be reset by bringing pdn= ?l? to ?h? only upon power up. note 21. this is the count of lrck ? ? from pmadc bit=?1?.
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 11 - ? timing diagram 1/fclk tclkl vih tclkh mclk vil 1/fs vih lrck vil tbck tbckl vih tbckh bick vil figure 2. clock timing tlrb lrck vih bick vil tlrs sdto 50%tvdd tbsd vih vil tblr tsds sdti vih vil tsdh figure 3. serial interface timing
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 12 - tcss csn vih cclk vil vih cdti vil vih vil c1 c0 r/w a4 tcckl tcckh tcds tcdh figure 4. write command input timing csn vih cclk vil vih cdti vil vih vil d3 d2 d1 d0 tcsw tcsh figure 5. write data input timing pmadc bit tpdv sdto 50%tvdd figure 6. power down & reset timing 1 tpd pdn vil figure 7. power down & reset timing 2
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 13 - operation overview ? system clock the external clocks required to operate the ak4665a are mc lk (256fs/512fs), lrck (fs) and bick. the master clock (mclk) should be synchronized with sampling clock (lrck). the phase between these clocks does not matter. the sampling frequency is selected by fs3-0 bits (refer to table 1). the frequency of mclk is detected automatically, and the internal master clock becomes the appropriate frequency. table 2 shows system clock example. fs3 fs2 fs1 fs0 fs 0 0 0 0 44.1khz default 0 0 0 1 32khz 0 0 1 0 48khz 1 0 0 0 22.05khz 1 0 0 1 16khz 1 0 1 0 24khz 1 1 0 0 11.025khz 1 1 0 1 8khz 1 1 1 0 12khz others n/a table 1. sampling frequency lrck mclk (mhz) bick (mhz) fs 256fs 512fs 64fs 8khz 2.048 4.096 0.512 11.025khz 2.8224 5.6448 0.7056 12khz 3.072 6.144 0.768 16khz 4.096 8.192 1.024 22.05khz 5.6448 11.2896 1.4112 24khz 6.144 12.288 1.536 32khz 8.192 16.384 2.048 44.1khz 11.2896 22.5792 2.8224 48khz 12.288 24.576 3.072 table 2. systems clock example external clocks (mclk, bick and lrck) are needed to operate adc, dac, alc2 or hp-amp. external clocks are also needed for each path setting of hp-amp (dachl, linhl, minhl, dachr, rinhr, minhr and hpmtn bits) and lineout (dacl, linl, minl, dacr, rinr and minr bits) when moff8 bit = ?0? or moff9 bit = ?0?. all external clocks (mclk, bick and lrck) should always be present whenever adc, dac, alc2 or hp-amp is in normal operation mode (pmadc bit = ?1?, pmdac bit = ?1?, pmlo=alc2 bits = ?1? or pmcp=pmhpl=pmhpr bits = ?1?). if these clocks are not provided, the ak4665a ma y draw excess current and will not operate properly because it utilizes these clocks for internal dynamic refresh of re gisters. if the external clocks are not present, the ak4665a should be placed in power-down mode (pdn pin = ?l? or pmadc=pmdac=alc2=pmcp=pmhpl=pmhpr bits = ?0?).
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 14 - for low sampling rates, outband noise causes s/n to degrade. s/n is improved by setting dfs bit to ?1?. table 3 shows s/n of dac output for both hp-amp and stereo-lineout. when dfs bit is ?1?, mclk needs 512fs. s/n (fs=8khz, bw=20khz, a-weighted) dfs fs mclk hp-amp lineout 0 8khz 48khz 256fs/512fs 84db 84db default 1 8khz 24khz 512fs 90db 88db table 3. relationship among fs, mclk frequency and s/n of hp-amp and lineout ? serial data interface the ak4665a interfaces with external systems via the bick, lrck, sdto and sdti pins. four data formats are available and are selected by setting dif1-0 bits (table 4). mode 0 of sdti is compatible with existing 16bit dac and digital filters. mode 1 of sdti is a 20bit version of mode 0. mode 2 of sdti is similar to akm adcs and many dsp serial ports. mode 3 is compatible with the i 2 s serial data protocol. in sdti modes 2 and 3, the following formats are also valid: 16-bit data followed by four zeros and 18-bit data followed by two zeros. in all modes, the serial data is msb first and 2?s complement format. mode dif1 dif0 sdto sdti bick lrck 0 0 0 20bit, msb justified 16bit, lsb justified 32fs h/l 1 0 1 20bit, msb justified 20bit, lsb justified 40fs h/l 2 1 0 20bit, msb justified 20bit, msb justified 40fs h/l default 3 1 1 iis (i 2 s) iis (i 2 s) 40fs l/h table 4. audio data format lrck bick ( 64fs ) sdto ( o ) 0 1 2 16 17 18 20 21 31 0 1 2 31 0 1 9 1 18 0 19 1 8 19 sdti ( i ) 1 1 4 0 1 5 12 11 1 0 lch dat a rch data don?t care don?t care 4 3 2 1 13 16 17 18 14 1 5 1 13 20 21 12 11 4 3 2 0 bick ( 32fs ) sdti ( i ) 0 1 2 8 9 10 15 0 1 2 0 1 5 1 14 7 8 12 11 14 6 5 4 13 3 2 1 0 8 9 10 15 7 8 12 11 14 6 5 4 13 3 2 1 0 1 5 14 1 5 sdto ( o ) 1 9 18 11 12 10 9 8 7 6 5 4 1 9 19 18 11 12 10 9 8 7 6 5 4 19 19 figure 8. mode 0 timing
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 15 - lrck bick ( 64fs ) sdto ( o ) 0 1 2 12 13 14 20 21 31 0 1 2 12 13 14 20 21 31 0 1 9 1 18 0 19 1 8 8 7 6 0 19 sdti ( i ) 1 1 8 0 19 12 11 1 18 0 19 12 11 lch data rch data don?t care don?t care 8 7 6 figure 9. mode 1 timing lrck bick(64fs) sdto(o) 0 1 2 15 16 17 18 31 0 1 2 0 19 1 18 3 19 18 19 sdti(i) 14 15 14 15 lch data rch data don?t care 4 0 20 19 30 15 2 31 30 16bit 1 0 15 16 3 don?t care 0 10 sdti(i) 16 17 0 16 17 don?t care 2 1 17 18bit 0 don?t care 21 sdti(i) 18 19 2 18 19 don?t care 4 3 19 20bit 1 0 don?t care 3 10 17 18 4 20 19 2 2 4 figure 10. mode 2 timing lrck bick(64fs) sdto ( o ) 0 1 2 3 16 17 18 31 0 1 2 0 19 1 18 3 19 18 sdti(i) 14 15 14 15 lch data rch data don?t care 4 0 20 19 30 2 31 30 16bit 10 31617 3 don?t care 0 1 sdti ( i ) 16 17 0 16 17 don?t care 2 1 18bit 0 don?t care 21 sdti ( i ) 18 19 2 18 19 don?t care 4 3 20bit 10 don?t care 3 1 21 18 4 20 19 20 2 40 21 figure 11. mode 3 timing
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 16 - ? digital high pass filter the ak4665a has a digital high pass filter (hpf) to cancel dc -offsets in adc. the cut-off frequency of the hpf is 3.4hz at fs=44.1khz. this filter scales with the sampling frequency (fs). ? mono-mic gain amplifier (micin pin) the ak4665a has a gain amplifier for mono-mic input. the gain of mic-amp is selected by mgain1-0 bits (see table 5). the input impedance is 60k ? (typ) at mgain1-0 bits = ?00?, ?01? and 30k ? (typ) at mgain1-0 bits = ?10?, ?11?. mgain1 bit mgain0 bit input gain input resistance 0 0 0db 60k ? (typ) default 0 1 ? 6db 60k ? (typ) 1 0 +6db 30k ? (typ) 1 1 +30db 30k ? (typ) table 5. mic input gain ? mic power (mpwr pin) when pmmp bit is ?1?, mpwr pin supplies power for the microphone. this output voltage is 2.0v(typ), and the load resistance is minimum 2k ? . capacitor must not be connected directly to mpwr pin (see figure 12). pmmp bit mpwr pin 0 hi-z default 1 output table 6. mic power mpwr 2k ? figure 12. mic block circuit
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 17 - ? input selector the ak4665a has 2-input selector for adc. adc input is selected by inl1, inr1 and inl2 bits. inl1 bit inr1 bit inl2 bit lch rch 1 1 0 ainl1 ainr1 default 0 0 1 micin micin table 7. input selector the input impedance of stereo line input (ainl1 and ainr1 pins) are 60k ? (typ). ? mono-record mode when adm bit is ?1?, adc lch data is output on both lch and rch of sdto. adm bit lch rch 0 l r default 1 l l table 8. mono-record mode
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 18 - ? alc1 operation (mic-alc) the alc1 (automatic level control) is done by alc1 block when alc1 bit is ?1?. 1. alc1 limiter operation during the alc1 limiter operation, when either lch or rch exceeds the alc1 limiter detection level (lmth1-0 bits: table 9), the ivol value (same value for lch and rch) is attenuated automatically by the alc1 limiter att step (lmat1-0 bits: table 10). when zelmn bit is ?0? (zero crossing de tection is enabled), the ivol value is changed by the alc1 limiter operation at the individual zero crossing points of lch and rch or at the zero crossing timeout. ztm1-0 bits set the zero crossing timeout period of both the alc1 limiter and recovery operation (table 11). when zelmn bit is ?1? (zero cro ssing detection is disabled), the ivol value is immediately (peri od: 1/fs) ch anged by the alc1 limiter operation. attenuation step is fixed to 1 step regardless as the setting of lmat1-0 bits. after completing the attenuation operation, unless alc1 bit is changed to ?0?, the operation repeats when the input signal level exceeds alc1 limiter detection level. lmth1 lmth0 alc1 limier detection level alc1 recovery waiting counter reset level 0 0 alc1 output ? 4.1dbfs ? 4.1dbfs > alc1 output ? 6.0dbfs default 0 1 alc1 output ? 6.0dbfs ? 6.0dbfs > alc1 output ? 8.5dbfs 1 0 alc1 output ? 8.5dbfs ? 8.5dbfs > alc1 output ? 12dbfs 1 1 alc1 output ? 10.1dbfs ? 10.1dbfs > alc1 output ? 14.5dbfs table 9. alc1 limiter detection level / recovery waiting counter reset level zelmn lmat1 lmat0 alc1 limiter att step 0 0 1 step 0.375db default 0 1 2 step 0.750db 1 0 4 step 1.500db 0 1 1 8 step 3.000db 1 x x 1 step 0.375db table 10. alc1 limiter att step (x: don?t care) alc1 zero cross timeout fs3 fs2 fs1 fs0 ztm=00 (default) ztm=01 ztm=10 ztm=11 0 0 0 0 384/fs (8.7ms) 768/fs (17.4ms) 1536/ fs (34.8ms) 3072/fs (69.7ms) default 0 0 0 1 256/fs (8.0ms) 512/fs (16.0m s) 1024/fs (32.0ms) 2048/fs (64.0ms) 0 0 1 0 384/fs (8.0ms) 768/fs (16.0m s) 1536/fs (32.0ms) 3072/fs (64.0ms) 1 0 0 0 192/fs (8.7ms) 384/fs (17.4m s) 768/fs (34.8ms) 1536/fs (69.7ms) 1 0 0 1 128/fs (8.0ms) 256/fs (16.0m s) 512/fs (32.0ms) 1024/fs (64.0ms) 1 0 1 0 192/fs (8.0ms) 384/fs (16.0m s) 768/fs (32.0ms) 1536/fs (64.0ms) 1 1 0 0 96/fs (8.7ms) 192/fs (17.4ms) 384/fs (34.8ms) 768/fs (69.7ms) 1 1 0 1 64/fs (8.0ms) 128/fs (16.0ms) 256/fs (32.0ms) 512/fs (64.0ms) 1 1 1 0 96/fs (8.0ms) 192/fs (16.0ms) 384/fs (32.0ms) 768/fs (64.0ms) others n/a table 11. alc1 zero crossing timeout period
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 19 - 2. alc1 recovery operation the alc1 recovery operation waits for wtm1-0 bits (table 12) to be set after completing the alc1 limiter operation. if the input signal does not exceed ?alc1 recovery waiting counter reset level? (table 9) during the wait time, the alc1 recovery operation is done. the ivol value (same value for lch and rch) is automatically incremented by rgain1-0 bits (table 13) up to the set reference level (table 14) with zero crossing detection which timeout period is set by ztm1-0 bits (table 11). the alc1 recovery operation is done at a period set by wtm1-0 bits. when zero cross is detected at both channels during the wait period set by wtm1-0 bits, the alc1 recovery operation waits until wtm1-0 period and the next recovery operation is done. the setting period of wtm1-0 bits should be the same as ztm1-0 bits or longer time. for example, when the current ivol value is 30h and rgain1-0 bits are set to ?01?, the ivol is changed to 32h by the alc1 limiter operation and then the input signal level is gained by 0.75db (=0.375db x 2). when the ivol value exceeds the reference level (ref7-0), the ivol values are not increased. when ?alc1 recovery waiting counter reset level (lmth1-0) output signal < alc limiter detection level (lmth1-0)? during the alc1 recovery operation, the waiting timer of alc1 recovery operation is reset. when ?alc1 recovery waiting counter reset level (lmth1-0) > output signal?, the waiting timer of alc1 recovery operation starts. the alc1 operation corresponds to the impulse noise. when the impulse noise is input, the alc1 recovery operation becomes faster than a normal recovery operation. when large noise is input to microphone instantaneously, the quality of small level in the large noise can be improved by this fast recovery operation. alc1 recovery time fs3 fs2 fs1 fs0 wtm=00 (default) wtm=01 wtm=10 wtm=11 0 0 0 0 384/fs (8.7ms) 768/fs (17.4ms) 1536/ fs (34.8ms) 3072/fs (69.7ms) default 0 0 0 1 256/fs (8.0ms) 512/fs (16.0m s) 1024/fs (32.0ms) 2048/fs (64.0ms) 0 0 1 0 384/fs (8.0ms) 768/fs (16.0m s) 1536/fs (32.0ms) 3072/fs (64.0ms) 1 0 0 0 192/fs (8.7ms) 384/fs (17.4m s) 768/fs (34.8ms) 1536/fs (69.7ms) 1 0 0 1 128/fs (8.0ms) 256/fs (16.0m s) 512/fs (32.0ms) 1024/fs (64.0ms) 1 0 1 0 192/fs (8.0ms) 384/fs (16.0m s) 768/fs (32.0ms) 1536/fs (64.0ms) 1 1 0 0 96/fs (8.7ms) 192/fs (17.4ms) 384/fs (34.8ms) 768/fs (69.7ms) 1 1 0 1 64/fs (8.0ms) 128/fs (16.0ms) 256/fs (32.0ms) 512/fs (64.0ms) 1 1 1 0 96/fs (8.0ms) 192/fs (16.0ms) 384/fs (32.0ms) 768/fs (64.0ms) others n/a table 12. alc1 recovery operation period rgain1 rgain0 gain step 0 0 1 step 0.375db default 0 1 2 step 0.750db 1 0 3 step 1.125db 1 1 4 step 1.500db table 13. alc1 recovery gain step
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 20 - ref7-0 gain(db) step ffh +41.25 feh +40.875 fdh +40.5 : : e2h +30.375 e1h +30.0 default e0h +29.625 : : 03h ? 53.25 02h ? 53.625 01h ? 54.0 0.375db 00h mute table 14. reference level at alc1 recovery operation
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 21 - 3. example for alc1 operation table 15 shows the examples of the alc1 setting. fs register name comment data 8khz 16khz 32khz 11.025khz 22.05khz 44.1khz 12khz 24khz 48khz lmth limiter detection level 00 ? 4.1dbfs ? 4.1dbfs ? 4.1dbfs zelmn limiter zero crossing detect ion 0 enable enable enable ztm1-0 zero crossing timeout period 00 8ms 8.7ms 8ms wtm1-0 recovery waiting period *wtm1-0 bits should be the same data as ztm1-0 bits 00 8ms 8.7ms 8ms ref7-0 maximum gain at recovery operation e1h +30db +30db +30db ivol7-0 gain of ivol 91h 0db 0db 0db lmat1-0 limiter att step 00 0.375db 0.375db 0.375db rgain1-0 recovery gain step 00 0.375db 0.375db 0.375db alc1 alc1 enable 1 en able enable enable table 15. example for the alc1 setting the following registers should not be changed during the alc1 operation. these bits should be changed after the alc1 operation is finished by alc1 bit = ?0? or pmadc bit = ?0?. - lmth, lmat1-0, wtm1-0, ztm1-0, rgain1-0, ref7-0, zelmn manual mode * the value of ivol should be the same or smaller than ref?s wr (ztm1-0, wtm1-0) wr (ref7-0) wr (ivol7-0) wr (lmat1-0, rgain1-0, zelmn, lmth1-0; alc1= ?1?) example: limiter = zero crossing enable recovery cycle = 8ms@8khz limiter and recovery step = 1 maximum gain = +30.0db limiter detection level = ? 4.1dbfs alc1 bit = ?1? (1) addr=05h, data=91h (2) addr=02h, data=00h (3) addr=04h, data=e1h alc1 operation (4) addr=03h, data=20h note : wr : write figure 13. registers set-up sequence at alc1 operation
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 22 - ? input digital volume (ivol: manual mode) the input digital volume becomes a manual mode when alc1 bit is ?0?. this mode is used in the case shown below. 1. after exiting reset state, set-up the registers for the alc1 operation (ztm1-0, lmth and etc) 2. when the registers for the alc1 operation (limiter period, recovery period and etc) are changed. for example; when the change of the sampling frequency. 3. when ivol is used as a manual volume. ivol7-0 bits set the gain of the volume control (table 16). th e ivol value is changed at zero crossing or timeout. zero crossing timeout period is set by ztm1-0 bits. if ivol7-0 bits are written during pmadc bit = ?0?, ivol operation starts with the written values at the end of the adc initialization cycle after pmadc bit is changed to ?1?. ivol7-0 gain (db) step ffh +41.25 feh +40.875 fdh +40.5 : : 92h +0.375 91h 0.0 default 90h ? 0.375 : : 03h ? 53.25 02h ? 53.625 01h ? 54 0.375db 00h mute table 16. input digital volume
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 23 - when writing to ivol7-0 bits continuously, the control register should be written by an interval more than zero crossing timeout. if not, the ivol is not changed since zero crossing counter is reset at every write operation. if the same register value as the previous write operation is written to ivol, th e write operation is ignored and zero crossing counter is not reset. therefore, ivol can be written by an interval less than zero crossing timeout. a lc1 bit a lc1 status disable enabl e disable ivol7-0 bits e1h(+ 30db ) inte rn al ivo l e1h(+ 30db ) e1(+30db) --> f1(+36db ) e1(+30db) (1) (2) figure 14. ivol value during alc1 operation (1) alc1 operation starts from the ivol value when alc1 bit is changed to ?1?. the wait time from alc1 bit = ?1? to alc1 operation start by ivol7-0 bits is at most recovery time (wtm1-0 bits) plus zero cross timeout period (ztm1-0 bits). (2) writing to ivol register (05h) is i gnored during alc1 operation. after alc1 is disabled, the ivol changes to the last written data by zero crossing or timeout. when alc1 is enabled again, alc1 bit should be set to ?1? by an interval more than zero crossing time out period after alc1 bit = ?0?. ? adc output on/off (sdto pin) sdto pin becomes ?l? when sdod bit is ?1?. sdod bit sdto pin 0 output default 1 ?l? table 17. adc output on/off ? digital loopback adc output data is internally passed to dac when loop bit is ?1?. the external input data to sdti pin is ignored. this operation is independent of sdod bit. loop bit dac input 0 sdti pin default 1 adc output table 18. digital loopback
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 24 - ? digital output volume (datt) the ak4665a has a channel-independent digital attenuator (256 levels, 0.5db step). this digital attenuator is placed before the d/a converter. attl/r7-0 bits set the attenuation level (0db to ? 127db or mute) for each channel (datt). at dattc bit = ?1?, attl7-0 bits control both lch and rch attenuation levels. at dattc bit = ?0?, attl7-0 bits control the lch level and attr7-0 bits control the rch level. attl/r7-0 attenuation ffh 0db feh ? 0.5db fdh ? 1.0db fch ? 1.5db : : : : 02h ? 126.5db 01h ? 127.0db 00h mute ( ? ) default table 19. digital volume code table the ats bit sets the transition time between set values of attl/r7-0 bits as either 1061/fs or 256/fs (table 20). when ats bit is ?0?, a soft transition between the set values oc curs (1062 levels). it takes 1061/fs (24ms@fs=44.1khz) from ?ffh? (0db) to ?00h? (mute). when pdn pin is ?l?, a ttl/r bits are initialized to ?00h?. the attl/r bits are ?00h? when pmdac bit is ?0?. when pmdac bit returns to ?1?, the a ttl/r bits fade to their current value. transition time between attl/r7-0 bits = 00h and ffh ats bit setting fs=8khz fs=44.1khz 0 1061/fs 133ms 24ms default 1 256/fs 32ms 6ms table 20. transition time setting of digital output volume
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 25 - ? soft mute (smute) soft mute operation is performed in the digital domain. when smute bit goes to ?1?, the output signal is attenuated by ? (?0?) via the cycle set by ats bit (table 20). when smute bit returns to ?0?, the mute is cancelled and the output attenuation gradually changes to 0db via the cycle set by ats bit. if the soft mute is cancelled within the cycle set by ats bit after starting the operation, the attenuation is discontinued and returned to 0db. the soft mute is effective for changing the signal source without stopping the signal transmission. smute bit a ttenuation ats bit attl/r7-0 bits - a nalog output gd gd (1) (2) (3) ats bit figure 15. soft mute function notes: (1) the output signal is attenuated until ? (?0?) by the cycle set by ats bit. (2) analog output corresponding to digital input has the group delay (gd). (3) if the soft mute is cancelled within the cycle set by ats bit, the attenuation is discontinued and returned to the setting value by the same cycle.
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 26 - ? de-emphasis filter (dem) the ak4665a includes a digital de-emphasis filter (tc = 50/15 s) by iir filter corresponding to three sampling frequencies (32khz, 44.1khz and 48khz). the de-emphasis filter is enabled by setting dem1-0 bits (table 21). dem1 dem0 de-emphasis 0 0 44.1khz 0 1 off default 1 0 48khz 1 1 32khz table 21. de-emphasis control ? bass boost function (boost) by controlling bst1-0 bits, the bass boost signal can be output from dac. the setting value is common in lch and rch (table 22). the frequency of bass boost filter scales sampling frequency. bst1 bst0 boost 0 0 off default 0 1 min 1 0 mid 1 1 max table 22. bass boost boost filter (fs=44.1khz) -5 0 5 10 15 20 10 100 1000 10000 frequency [hz] level [db] max mid min figure 16. bass boost frequency (fs=44.1khz)
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 27 - ? external analog input (lin, rin, min pins) the input signals from lin/rin/min pins can be output fr om headphone and lineout. lin/rin/min input buffers are 2 nd order lpf (fc=50khz(typ)) in order to attenuate the high frequency noise of external analog input signals. dc component of input signal should be cut by external capacitor. the cut-off frequency (fc) of hpf depends on the internal input resistance (ri) and the external capacitor value (c): fc=1/(2 ric). the input resistance is 200k ? 50%, the gain is 0db(typ) for both lineout and hp-amp (hpg=ling bits = ?0?). when hpg bit = ?1? and ling bit = ?0?, the gain of hp-amp is ? 5.5db(typ). when hpg bit = ?0? and ling bit = ?1?, the gain of lin/rin hpl/hpr paths are ? 12db(typ). lin/rin/min input buffers powered-up when either bits of pmhpl, pmhpr and pmlo bits become ?1?. lineout lin/rin/min pin ri ? + a k4665 a hp-amp c figure 17. external analog input circuit
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 28 - ? alc2 operation (lout, rout pins) the alc2 (automatic level control) of stereo line out is done by alc2 block when alc2 bit is ?1?. the gain of alc2 block is fixed to 0db when alc2 bit is ?0?. (1) alc2 limiter operation during the alc2 limiter operation, when the alc2 output level exceeds the alc2 limiter detection level (lmthp bit: table 23), the volume value of alc2 is attenuated automatically by the amount defined by the alc2 limiter att step (lmatp1-0 bits: table 24). the volume value is changed without zero crossing detection. ltmp1-0 bits (table 25) set the alc2 limiter operation period. lmthp alc2 limiter detection level alc2 recovery waiting counter reset level 0 alc2 output ? 7.5dbv ? 7.5dbv > alc2 output ? 9.5dbv default 1 alc2 output ? 11.5dbv ? 11.5dbv > alc2 output ? 13.5dbv table 23. alc2 limiter detection level / recovery waiting counter reset level lmatp1 lmatp0 att step 0 0 1 step 0.5db default 0 1 2 step 1.0db 1 0 3 step 1.5db 1 1 4 step 2.0db table 24. alc2 limiter att step alc2 limiter time fs3 fs2 fs1 fs0 ltmp=00 (default) ltmp=01 ltmp= 10 ltmp=11 0 0 0 0 6/fs (136 s) 12/fs (272 s) 24/fs (544 s) 48/fs (1088 s) default 0 0 0 1 4/fs (125 s) 8/fs (250 s) 16/fs (500 s) 32/fs (1000 s) 0 0 1 0 6/fs (125 s) 12/fs (250 s) 24/fs (500 s) 48/fs (1000 s) 1 0 0 0 3/fs (136 s) 6/fs (272 s) 12/fs (544 s) 24/fs (1088 s) 1 0 0 1 2/fs (125 s) 4/fs (250 s) 8/fs (500 s) 16/fs (1000 s) 1 0 1 0 3/fs (125 s) 6/fs (250 s) 12/fs (500 s) 24/fs (1000 s) 1 1 0 0 1.5/fs (136 s) 3/fs (272 s) 6/fs (544 s) 12/fs (1088 s) 1 1 0 1 1/fs (125 s) 2/fs (250 s) 4/fs (500 s) 8/fs (1000 s) 1 1 1 0 1.5/fs (125 s) 3/fs (250 s) 6/fs (500 s) 12/fs (1000 s) others n/a table 25. alc2 limiter operation period (2) alc2 recovery operation the alc2 recovery operation waits for wtmp1-0 bits (table 26) to be set after completing the alc2 limiter operation. if the input signal does not exceed ?alc2 recovery waiting counter reset level? (lmthp bit) during the wait time, the alc2 recovery operation is done. the alc2 value is automatically incremented by rgainp bit (table 27) up to the set reference level (refp5-0 bits: table 28). the alc2 recovery operation is done at a period set by wtmp1-0 bits. when zero cross is detected at both channels during the wait period set by wtm1-0 bits, the alc recovery operation waits until wtm1-0 period and the next recovery opera tion is done. the setting period of wtm1 -0 bits should be the same as ztm1-0 bits or longer time. when moff9 bit is ?0?, the volume value is incremented with soft transition. the soft transition time is set by pts1-0 bits (table 39). the wtmp1- 0 bits should be set to the same period as pts1-0 bits or longer. when moff9 bit is ?1?, the volume increase immediately. during the alc2 recovery operation, the alc2 limiter opera tion starts immediately as soon as the alc2 output level exceeds the alc2 limiter detection level (lmthp bit).
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 29 - when ?alc2 recovery waiting counter reset level alc2 output signal level < alc2 limiter detection level? during the alc2 recovery operation, the waiting timer of alc2 recovery operation is reset. when ?alc2 recovery waiting counter reset level > alc2 output signal level?, the waiting timer of alc1 recovery operation starts. alc2 recovery time fs3 fs2 fs1 fs0 wtmp=00 (default) wtmp=01 wtmp=10 wtmp=11 0 0 0 0 768/fs (17.4ms) 1536/fs (34.8ms) 3072/fs (69.7ms) 24576/fs (557ms) default 0 0 0 1 512/fs (16.0ms) 1024/fs (32.0ms) 2048/fs (64.0ms) 16384/fs (512ms) 0 0 1 0 768/fs (16.0ms) 1536/fs (32.0ms) 3072/fs (64.0ms) 24576/fs (512ms) 1 0 0 0 384/fs (17.4ms) 768/fs (34.8m s) 1536/fs (69.7ms) 12288/fs (557ms) 1 0 0 1 256/fs (16.0ms) 512/fs (32.0ms) 1024/fs (64.0ms) 8192/fs (512ms) 1 0 1 0 384/fs (16.0ms) 768/fs (32.0m s) 1536/fs (64.0ms) 12288/fs (512ms) 1 1 0 0 192/fs (17.4ms) 384/fs (34.8m s) 768/fs (69.7ms) 6144/fs (557ms) 1 1 0 1 128/fs (16.0ms) 256/fs (32.0m s) 512/fs (64.0ms) 4096/fs (512ms) 1 1 1 0 192/fs (16.0ms) 384/fs (32.0m s) 768/fs (64.0ms) 6144/fs (512ms) others n/a table 26. alc2 recovery operation period rgainp gain step 0 1 step 0.5db default 1 2 step 1.0db table 27. alc2 recovery gain step refp5-0 gain(db) step 3fh +19.5 3eh +19.0 3dh +18.5 3ch +18.0 default : : 19h +0.5 18h 0.0 17h ? 0.5 : : 02h ? 11.0 01h ? 11.5 00h ? 12.0 0.5db table 28. reference level at alc2 recovery operation
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 30 - (3) example for alc2 operation table 29 shows the examples of the alc2 setting. the alc2 operation starts from 0db. fs register name comment data 8khz 16khz 32khz 11.025khz 22.05khz 44.1khz 12khz 24khz 48khz lmthp limiter detection level 1 ? 11.5dbv ? 11.5dbv ? 11.5dbv ltmp1-0 maximum gain at recovery operation 10 500 s 544 s 500 s wtmp1-0 recovery waiting period 11 512ms 557ms 512ms refp7-0 maximum gain at recovery operation 30h +12db +12db +12db lmatp1-0 limiter att step 00 0.5db 0.5db 0.5db rgainp recovery gain step 0 0.5db 0.5db 0.5db pts1-0 alc2 recovery transition time 11 128ms 139ms 128ms alc2 alc2 enable bit 1 enable enable enable table 29. example for the alc2 setting the following registers should not be changed during the alc2 operation. these bits should be changed after the alc2 operation is finished by alc2 bit is ?0? or pmlo bit is ?0?. - lmthp, ltmp1-0, lmatp1-0, wtmp1-0, rgainp, refp5-0, pts1-0 alc2=off wr (lmatp1-0, rgainp, wtmp1-0) wr (refp5-0) alc2 o p eration wr (alc2= ?1?) exa mple: limiter cycle = 544 s @ fs=44.1khz recovery cycle = 557ms @ fs= 44.1khz limiter and recovery step = 1 maximu m gain = +12db limiter detection level = ? 11.5dbv recovery transition time = 139ms @ fs=44.1khz alc2 bit = ?1? (1) addr=12h, data=18h (3) addr=11h, data=30h (5) addr=12h, data=38h wr (lmthp, ltmp1-0) (2) addr=13h, data=18h wr (pts1-0) (4) addr =14h, data=c0h note : wr : write figure 18. registers set-up sequence at alc2 operation
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 31 - ? output analog volume (lout, rout pins) when the lmute bit is ?0?, atts3-0 bits (0db ? 30db, 2db step, table 30) control the lout/rout output level. some pop noise occurs at the changing of output volume of lout/rout. lmute atts3-0 attenuation fh 0db eh ? 2db dh ? 4db ch ? 6db : : : : 1h ? 28db 0 0h ? 30db 1 x mute default table 30. lout/rout volu me att (x: don?t care) ? stereo line output (lout, rout pins) the common voltage is vcom, and the load resistance is min. 10k ? . stereo lineout is powered-up when pmlo bit is ?1?. the on/off of each path is set by dacl, linl, minl, dacr, rinr and minr bits. when alc2 bit is ?0? and atts3-0 bits is ?fh?(0db), the summation gain of each path is 0db (typ). lout/ rout pi n lin/rin pin min pin linl/rinr bi t minl/minr bi t da cl/da cr bi t dacl/dacr alc2 opga figure 19. lout/rout summation circuit (l+r)/2 signal of dac is output from lout and rout pins when lom bit is ?1?. dacl lom bit lout pin 0 x path off default 0 l 1 1 (l+r)/2 table 31. line output mode (lch) dacr lom bit rout pin 0 x path off default 0 r 1 1 (l+r)/2 table 32. line output mode (rch)
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 32 - ? headphone output (hpl/hpr pins) power supply voltage for headphone amplifiers is applied fr om hvdd pin for the positive supply and the negative supply generated by the internal charge pump circuit. the headphone amplifier is single-ended outputs and centered on 0v (avss). therefore, the capacitor for ac-coupling can be removed. the minimum load resistance is 16 ? . hpg bit set the output voltage (table 33). hpg bit output voltage output power 0 1.5vpp@0dbfs 17mw@16 ? default 1 2.0vpp@ ? 3dbfs 31mw@16 ? table 33. headphone output voltage / power the headphone output is enabled when hpmtn bit is ?1? and muted when hpmtn bit is ?0?. the mute on/off time are set by pts1-0 bits (table 39) when moff8 bit is ?0?. when moff8 bit is ?1?, the on/off is done immediately. when pmhpl and pmhpr bits are ?0?, the headphone amplifiers are powered-down completely. at that time, the hpl and hpr pins are avss voltage. the power-up/down time are set by put1-0 bits (table 38) when moff0 bit is ?0?. when moff0 bit is ?1?, the power up/down is done immediately. pmhpl/r bits hpmtn bit hp-amp 0 x power-down default 0 power-up & mute 1 1 power-up & output table 34. headphone output states the on/off of each path is set by dachl, linhl, minhl, dachr, rinhr and minhr bits. the summation gain of each path is 0db (typ) at hpg bit = ?0? and +5.5db (typ) at hpg bit = ?1?. hpl/hp r pin lin/rin pin min pin linhl/ rinhr bi t minhl/ minhr bi t da chl/ da chr bit dacl/dacr figure 20. the summation circuit of headphone output (l+r)/2 signal of dac is output from hpl and hpr pins when hpm bit is ?1?. dachl hpm bit hpl pin 0 x path off default 0 l 1 1 (l+r)/2 table 35. headphone output mode (lch) dachr hpm bit hpr pin 0 x path off default 0 r 1 1 (l+r)/2 table 36. headphone output mode (rch)
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 33 - ? transition time the power-up/down time of hp-amp at the change of pmhpl/r bits is set by put1-0 bits (table 38). the mute on/off timing of hp-amp, the on/off timing of output path for hpl/hpr and lout/rout, and the gain changing at alc2 recovery operation are changed by the soft transition respectively. the transition time is set by pts1-0 bits (table 39). the register value of same address must be changed by an interval more than transition time. the enable/disable for the soft transition is set by moff0, moff8 and moff9 bits (table 37). the soft transition is disabled while these bits are ?1?, and on/off is done immediately. as shown in table 37, if the soft transition is enabled, the re gister value of same address must be changed by an interval more than trans ition time. the write operation is ignor ed if the same values are written as the pr evious write operation. address register name enable/disable put1-0 bits 00h pmhpl, pmhpr bits moff0 bit 08h dachl, linhl, minhl, dachr, rinhr, minhr, hpmtn bits moff8 bit pts1-0 bits 09h dacl, linl, rinr, minl, dacr, minr bits moff9 bit table 37. registers with transition time power-up/down time fs3 fs2 fs1 fs0 put=00 (default) put=01 put=10 put=11 0 0 0 0 770/fs (17.5ms) 1538/fs (34.9ms) 3074/fs (69.7ms) 6146/fs (139ms) default 0 0 0 1 514/fs (16.1ms) 1026/fs (32.1m s) 2050/fs (64.1ms) 4098/fs (128ms) 0 0 1 0 770/fs (16.1ms) 1538/fs (32.1m s) 3074/fs (64.1ms) 6146/fs (128ms) 1 0 0 0 386/fs (17.5ms) 770/fs (34.9m s) 1538/fs (69.8ms) 3074/fs (139ms) 1 0 0 1 258/fs (16.1ms) 514/fs (32.1m s) 1026/fs (64.1ms) 2050/fs (128ms) 1 0 1 0 386/fs (16.1ms) 770/fs (32.1m s) 1538/fs (64.1ms) 3074/fs (128ms) 1 1 0 0 194/fs (17.6ms) 386/fs (35.0m s) 770/fs (69.8ms) 1538/fs (140ms) 1 1 0 1 130/fs (16.3ms) 258/fs (32.3m s) 514/fs (64.3ms) 1026/fs (128ms) 1 1 1 0 194/fs (16.2ms) 386/fs (32.2m s) 770/fs (64.2ms) 1538/fs (128ms) others n/a table 38. hp-amp power-up/down time transition time fs3 fs2 fs1 fs0 pts=00 (default) pts=01 pts=10 pts=11 0 0 0 0 768/fs (17.4ms) 1536/fs (34.8ms) 3072/fs (69.7ms) 6144/fs (139ms) default 0 0 0 1 512/fs (16.0ms) 1024/fs (32.0m s) 2048/fs (64.0ms) 4096/fs (128ms) 0 0 1 0 768/fs (16.0ms) 1536/fs (32.0m s) 3072/fs (64.0ms) 6144/fs (128ms) 1 0 0 0 384/fs (17.4ms) 768/fs (34.8m s) 1536/fs (69.7ms) 3072/fs (139ms) 1 0 0 1 256/fs (16.0ms) 512/fs (32.0m s) 1024/fs (64.0ms) 2048/fs (128ms) 1 0 1 0 384/fs (16.0ms) 768/fs (32.0m s) 1536/fs (64.0ms) 3072/fs (128ms) 1 1 0 0 192/fs (17.4ms) 384/fs (34.8m s) 768/fs (69.7ms) 1536/fs (139ms) 1 1 0 1 128/fs (16.0ms) 256/fs (32.0m s) 512/fs (64.0ms) 1024/fs (128ms) 1 1 1 0 192/fs (16.0ms) 384/fs (32.0m s) 768/fs (64.0ms) 1536/fs (128ms) others n/a table 39. hp-amp mute on/off, path on/off & alc2 recovery transition time
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 34 - ? charge pump circuit the internal charge pump circuit generates negative voltage from hvdd voltage. the generated voltage is used to headphone amplifier. when pmcp bit is set to ?1?, the char ge pump circuit is powered-up. all clocks (mclk, bick and lrck) should be supplied at this time. the power-up time of charge pump circuit depends on fs3-0 bits (table 40). fs3 fs2 fs1 fs0 fs power up time of charge pump circuit 0 0 0 0 44.1khz 512/fs = 11.6ms default 0 0 0 1 32khz 256/fs = 8.0ms 0 0 1 0 48khz 512/fs = 10.7ms 1 0 0 0 22.05khz 256/fs = 11.6ms 1 0 0 1 16khz 128/fs = 8.0ms 1 0 1 0 24khz 256/fs = 10.7ms 1 1 0 0 11.025khz 128/fs = 11.6ms 1 1 0 1 8khz 64/fs = 8.0ms 1 1 1 0 12khz 128/fs = 10.7ms others n/a n/a table 40. power up time of charge pump circuit ? system reset the ak4665a should be reset once by bringing pdn pin ?l? upon power-up. after exiting reset, all blocks (vcom, adc, dac, hpl, hpr, lineout and charge pump circuit) switch to the power-down state. the contents of the control register are maintained until the reset is done. adc exits reset and power down state after pmadc bit is cha nged to ?1?, and then adc is powered-up and the internal timing starts clocking by lrck edge. adc is in power-down mode until mclk and lrck are input. dac also exits reset and power down state when mclk and lrck are input after pmdac bit is changed to ?1?.
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 35 - ? power-up/down sequence 1) adc (micin) power supply clock input pmadc bit a dc internal state micin pin pd(power-down)init cycle normal operation (7) 2081/fs sdto pin (8) gd (6) (5) pd (8) gd (hi-z) (hi-z) don?t care pmvcm bit (1) >150ns (4) >0 fs3-0, dfs bits (2) >0 (3) >0 don?t care pdn pi n xh, x 0h, 0 0h, 0 figure 21. power-up/down sequence of adc (1) pdn pin should be set to ?h? at least 150ns after the power is supplied. (2) fs3-0 and dfs bits should be set after pdn pin goes to ?h?. (3) pmvcm bit should be changed to ?1? after fs3-0 and dfs bits are set. (4) pmadc bit should be changed to ?1? after pmvcm bit is changed to ?1?. (5) external clocks (mclk, bick and lrck) are needed to operate adc. (6) when pmadc bit is changed to ?1?, micin pin is biased to vcom voltage. rising time constant is determined by input capacitor for ac coupling and input resistance. in case of 0.22f input capacitor, time constant is = 0.22f x 30k ? = 6.6ms (typ) at mgain1 bit = ?1? = 0.22f x 60k ? = 13.2ms (typ) at mgain1 bit = ?0? (7) the analog part of adc is initialized during 2081/fs (=47ms@fs=44.1khz) after exiting the power-down state. sdto is ?l? at that time. (8) digital output corresponding to analog input has the group delay (gd) of 17.0/fs(=385s@fs=44.1khz).
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 36 - 2) adc (line in: in case of common jack with headphone) power supply clock input pmadc bit a dc internal state a inl1/r1 pins pd(power-down) init cycle normal operation (8) 2081/fs sdto pin (9) gd (7) (5) pd (9) gd (hi-z) (hi-z) don?t care pmvcm bit (1) >150ns (6) >0 fs3-0, dfs bits nvss pin (2) >0 (3) >0 (4) >0 0v ? hvdd don?t care 0v pdn pin pmcp bit xh, x 0h, 0 0h, 0 (10) pmhpl/r bits (11) figure 22. power-up/down sequence of adc (1) pdn pin should be set to ?h? at least 150ns after the power is supplied. (2) fs3-0 and dfs bits should be set after pdn pin goes to ?h?. (3) pmvcm bit should be changed to ?1? after fs3-0 and dfs bits are set. (4) pmcp bit should be changed to ?1? after pmvcm bit is changed to ?1?. the charge pump circuit is powered-up and nvss pin goes to ?hvdd voltage according to the setting of fs3-0 and dfs bits. (5) external clocks (mclk, bick and lrck) are needed to operate the charge pump circuit and adc. (6) pmadc bit should be changed to ?1? after nvss pin goes to ?hvdd voltage. (7) when pmadc bit is changed to ?1?, ainl1/r1 pins are biased to vcom voltage. rising time constant is determined by input capacitor for ac coupling and input resistance. in case of 1f input capacitor, time constant is = 1f x 60k ? = 60ms (typ) (8) the analog part of adc is initialized during 2081/fs (=47ms@fs=44.1khz) after exiting the power-down state. sdto is ?l? at that time. (9) digital output corresponding to analog input has the group delay (gd) of 17/fs (=385s@fs=44.1khz). (10) when pmcp bit is changed to ?0?, the charge pump circuit is powered-down and nvss pin becomes 0v. falling time constant is determined by capacitor and internal resistance (typ 17.5k ? ). in case of 2.2f capacitor, time constant is = 2.2f x 17.5k ? = 38.5ms (typ) (11) when pmhpl/r bits = ?0?, hpl/r pins are connected to avss with internal pull-down resistance (typ 100k ? ).
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 37 - 3) dac hp-amp power supply pdn pin pmvcm bit clock input (5) sdti pin pmdac bit dac internal state pd normal operation hpl/r pins pmhpl/r bits (7) a ttl/r7-0 bits 00h(mute) ffh(0db) (9) gd (10) 1061/fs pd 00h(mute) (9) (10) don?t care hpmtn bit (1) >150ns (3) >0 fs3-0, dfs bits xh, x 0h, 0 0h, 0 put1-0 bits pts1-0 bits xx, xx 00, 00 00, 00 pmcp bit (6) >0 dachl bit dachr bit (4) >0 nvss pin 0v ? hvdd 0v (8) (12) (13) don?t care hp-amp state pd normal operation pd mt mt (2) >0 (14) (11) figure 23. power-up/down sequence of dac and hp-amp (1) pdn pin should be set to ?h? at least 150ns after the power is supplied. (2) fs3-0, dfs, put1-0 and pts1-0 bits should be set after pdn pin goes to ?h?. (3) pmvcm bit should be changed to ?1? after fs 3-0, dfs, put1-0 and pts1-0 bits are set. (4) dachl and dachr bits should be changed to ?1? after pmvcm bit is changed to ?1?. each path is switched-on during the transition time set by fs3-0 and pts1-0 bits. (5) external clocks (mclk, bick and lrck) are needed to operate the charge pump circuit, hp-amp or dac. external clocks are also needed for each path (dachl, linhl, minhl, dachr, rinhr, minhr and hpmtn bits) setting. (6) pmcp, pmdac, pmhpl and pmhpr bits should be changed to ?1? after dachl and dachr bits are changed to ?1?. when pmcp bit is changed to ?1?, the charge pump circuit is powered-up and nvss pin goes to ? hvdd voltage according to the setting of fs3-0 and dfs bits (7) after power-up of the charge pump circuit, hp-amp is pow ered-up. rising time of hp-amp is determined by fs3-0, dfs and put1-0 bits. (8) hpmtn bit should be changed to ?1? to release the mute after hp-amp is powered-up. the transition time of mute release is determined by fs3-0,dfs and pts1-0 bits. (9) digital output corresponding to analog input has the group delay (gd) of 17. 5/fs (=397s@fs=44.1khz). (10) the transition time for digital volume is set by at s bit. the initial value is 1061/fs (=24ms@fs=44.1khz). (11) hpmtn bit should be changed to ?0? to mute hp-amp. (12) after the transition time for mute, pmdac, pmhpl and pmhpr bits should be changed to ?0? to power-down of dac and hp-amp. (13) after power-down of the hp-amp, pmcp bit should be changed to ?0? to power-down the charge pump circuit. falling time constant is determined by external capacitor connected with nvss pin and internal resistance (typ 17.5k ? ). in case of 2.2f capacitor, time constant is = 2.2f x 17.5k ? = 38.5ms (typ) (14) clocks should be stopped after pmcp bit is changed to ?0?.
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 38 - 4) dac line out power supply pdn pin pmvcm bit clock input (4) sdti pin pmdac bit dac internal state pd(power-down) normal operation pmlo bit a ttl/r7-0 bit 00h(mute) ffh(0db) lout/rout pins (5) lmute, a tts3-0 bits 10h(mute) 0fh(0db) (6) gd (7) 1061/fs (hi-z) pd 00h(mute) (hi-z) (5) (6) (7) don?t care dacl, dacr bits (1) >150ns (2) >0 (3) >0 don?t care 10h figure 24. power-up/down sequence of dac and line out (1) pdn pin should be set to ?h? at least 150ns after the power is supplied. (2) dacl and dacr bits should be changed to ?1? after pdn pin goes to ?h?. each path is switched-on during the transition time set by fs3-0 and pts1-0 bits. (3) pmdac and pmlo bits should be changed to ?1? after dacl and dacr pins are changed to ?1?. (4) external clocks (mclk, bick and lrck) are needed to operate dac. external clocks are also needed for each path (dacl, linl, minl, dacr, rinr and minr bits) setting. (5) when pmlo bit is changed to ?1?, pop noise is output from lout/rout pins. (6) digital output corresponding to analog input has the group delay (gd) of 17. 5/fs (=397s@fs=44.1khz). (7) the transition time for digital volume is set by ats bit. the initial value is 1061/fs (=24ms@fs=44.1khz).
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 39 - 5) lin/rin/min hp-amp power supply pdn pin pmvcm bit clock input (5) hpl/r pins pmhpl/r bits (8) don?t care hpmtn bit (1) >150ns (3) >0 fs3-0, dfs bits xh, x 0h, 0 0h, 0 put1-0 bits pts1-0 bits xx, xx 00, 00 00, 00 pmcp bit (6) >0 linhl, minhl, rinhr, minhr bits (4) >0 nvss pin 0v ? hvdd 0v (9) (11) (12) don?t care hp-amp state pd normal operation pd mt mt (2) >0 (13) lin/rin/min pins (7) (hi-z) (hi-z) (10) figure 25. power-up/down sequence of lin/rin/min and hp-amp (1) pdn pin should be set to ?h? at least 150ns after the power is supplied. (2) fs3-0, dfs, put1-0 and pts1-0 bits should be set after pdn pin goes to ?h?. (3) pmvcm bit should be changed to ?1? after fs 3-0, dfs, put1-0 and pts1-0 bits are set. (4) linhl, minhl, rinhr and minhr bits should be changed to ?1? after pmvcm bit is changed to ?1?. each path is switched-on during the transition time set by fs3-0 and pts1-0 bits. (5) external clocks (mclk, bick and lrck) are needed to operate the charge pump circuit and hp-amp. external clocks are also needed for each path (dachl, linhl, minhl, dachr, rinhr, minhr and hpmtn bits) setting. (6) pmcp, pmhpl and pmhpr bits should be changed to ?1? after linhl, minhl, rinhr and minhr bits are changed to ?1?. when pmcp bit is changed to ?1?, the charge pump circuit is powered-up and nvss pin goes to ? hvdd voltage according to the setting of fs3-0 and dfs bits. (7) when pmhpl, pmhpr or pmlo bit is changed to ?1?, lin, rin and min pins are biased to vcom voltage. rising time constant is determined by capacitor for ac coupling and input resistance 200k ? (typ). in case of 0.047f input capacitor, time constant is = 0.047f x 200k ? = 9.4ms (typ) (8) after power-up the charge pump circuit, hp-amp is powered-up. rising time of hp-amp is determined by fs3-0,dfs and put1-0 bits. (9) hpmtn bit should be changed to ?1? to release the mute after hp-amp is powered-up. the transition time of mute release is determined by fs3-0,dfs and pts1-0 bits. (10) hpmtn bit should be changed to ?0? to mute hp-amp. (11) after the transition time for mute, pmhpl and pmhpr bits should be changed to ?0? to power-down of hp-amp. (12) after power-down of the hp-amp, pmcp bit should be changed to ?0? to power-down of the charge pump circuit. falling time constant is determined by external capacitor connected with nvss pin and internal resistance (typ 17.5k ? ). in case of 2.2f capacitor, time constant is = 2.2f x 17.5k ? = 38.5ms (typ) (13) clocks should be stopped after pmcp bit is changed to ?0?.
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 40 - ? serial control interface internal registers may be written via the 3-wire p inte rface pins (csn, cclk and cdti). the data on this interface consists of chip address (2bits, fixed to ?10?), read/write ( 1bit, fixed to ?1?, write only), register address (msb first, 5bits) and control data (msb first, 8bits). data is clocked in on the rising edge of cclk. for write operations, data is latched on the rising edge of 16th clock of cclk. the clock speed of cclk is 5mhz (max). the value of internal registers is initialized at pdn= ?l?. cdti cclk csn c1 0 1234567 8 9 10 11 12 13 14 15 d4 d5 d6 d7 a1 a2 a3 a4 r/w c0 a0 d0 d1 d2 d3 c1-c0: chip address (fixed to ?10?) r/w: read/write (fixed to ?1?: write only) a4-a0: register address d7-d0: control data figure 26. control interface
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 41 - ? register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management pmcp 0 pmlo pmhpr pmhpl pmdac pmadc pmvcm 01h input select moff0 0 pmmp adm 0 inr1 inl2 inl1 02h timer select mgain1 mgain0 ztm1 ztm0 wtm1 wtm0 0 0 03h alc1 mode control 1 rgain1 lmth1 alc1 zelmn lmat1 lmat0 rgain0 lmth0 04h alc1 mode control 2 ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 05h ivol control ivol7 ivol6 i vol5 ivol4 ivol3 ivol2 ivol1 ivol0 06h mode control 1 0 0 0 ats hpm dif1 dif0 dfs 07h dac control 0 0 smute dattc bst1 bst0 dem1 dem0 08h hp output select moff8 hpmtn minhr rinhr dachr minhl linhl dachl 09h line output select moff9 lom minr dacr minl rinr linl dacl 0ah dac lch att attl7 attl6 a ttl5 attl4 attl3 attl2 attl1 attl0 0bh dac rch att attr7 attr6 attr5 attr4 attr3 attr2 attr1 attr0 0ch lineout att 0 0 0 lmute atts3 atts2 atts1 atts0 0dh test 1 test7 test6 test5 test4 test3 test2 test1 test0 0eh test 2 test7 test6 test5 test4 test3 test2 test1 test0 0fh test 3 test7 test6 test5 test4 test3 test2 test1 test0 10h test 4 test7 test6 test5 test4 test3 test2 test1 test0 11h alc2 mode control 1 0 0 refp5 refp4 refp3 refp2 refp1 refp0 12h alc2 mode control 2 hpg ling alc2 wtmp1 wtmp0 lmatp1 lmatp0 rgainp 13h mode control 2 0 0 0 lmthp ltmp1 ltmp0 sdod loop 14h mode control 3 pts1 pts0 put1 put0 fs3 fs2 fs1 fs0 all registers inhibit writing at pdn pin = ?l?. note: unused bits must contain a ?0? value. note: for addresses from 0dh to 10h and from 15h to 1fh, ?0?data must be written.
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 42 - ? register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management pmcp 0 pmlo pmhpr pmhpl pmdac pmadc pmvcm default 0 0 0 0 0 0 0 0 pmvcm: power management for vcom block 0: power off (default) 1: power on pmadc: power management for mic-amp and adc blocks 0: power off (default) 1: power on mclk should be present when pmadc bit is ?1?. pmdac: power management for dac block 0: power off (default) 1: power on when pmdac bit is changed from ?0? to ?1?, dac is powered-up to the current register values (att value, sampling rate, etc). pmhpl: power management for lch of headphone amp 0: power off (default). hpl pin becomes avss (0v). 1: power on pmhpr: power management for rch of headphone amp 0: power off (default). hpr pin becomes avss (0v). 1: power on pmlo: power management for stereo lineout 0: power off (default). lout and rout pins become hi-z. 1: power on pmcp: power management for charge pump circuit 0: power off (default) 1: power on all blocks can be powered-down by setting pdn pin to ?l? regardless of register values setting. in this case, all control register values are initialized. when pmvcm, pmadc, pmdac, pmhpl, pmhpr, pmlo and pmcp bits are ?0?, all blocks are powered-down. the register values remain unchanged. power supply current is 100 a(typ) in this case. for fully shut down (typ. 1 a), pdn pin should be ?l?.
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 43 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h input select moff0 0 pmmp adm 0 inr1 inl2 inl1 default 0 0 0 0 0 1 0 1 inl1: select on/off of lch line input 0: off 1: on (default) inl2: select on/off of mono mic input 0: off (default) 1: on inr1: select on/off of rch line input 0: off 1: on (default) adm: mono recording mode (table 8) 0: stereo (default) 1: mono when adm bit is ?1?, adc lch data is output on both lch and rch of sdto. pmmp: power management for mpwr pin 0: power down: hi-z (default) 1: power up moff0: soft transition for changing pmhpl, pmhpr bits 0: enable (default) 1: disable addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h timer select mgain1 mgain0 ztm1 ztm0 wtm1 wtm0 0 0 default 0 0 0 0 0 0 0 0 wtm1-0: alc1 recovery waiting period (table 12) ztm1-0: alc1 zero crossing timeout period (table 11) mgain1-0: mic-amp gain (table 5)
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 44 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h alc1 mode control 1 rgain1 lmth1 alc1 zelmn lmat1 lmat0 rgain0 lmth0 default 0 0 0 0 0 0 0 0 lmth1-0: alc1 limiter detection level / recovery waiting counter reset level (table 9) rgain1-0: alc1 recovery gain step (table 13) lmat1-0: alc1 limiter att step (table 10) zelmn: zero crossing det ection enable at alc1 limiter operation 0: enable (default) 1: disable alc1: alc1 enable 0: alc1 disable (default) 1: alc1 enable alc1 is enabled at alc1 bit is ?1?. addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h alc1 mode control 2 ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 default 1 1 1 0 0 0 0 1 ref7-0: reference value at alc1 recovery operation (table 14) addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h ivol control ivol7 ivol6 i vol5 ivol4 ivol3 ivol2 ivol1 ivol0 default 1 0 0 1 0 0 0 1 ivol7-0: input digital volume (table 16) addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h mode control 0 0 0 ats hpm dif1 dif0 dfs default 0 0 0 0 0 1 0 0 dfs: sampling speed mode (table 1) dif1-0: audio interface format (table 4) default: ?10? (mode 2) hpm: mono output select of headphone (table 35,table 36) ats: digital attenuator transition time setting (table 20)
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 45 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h dac control 0 0 smute dattc bst1 bst0 dem1 dem0 default 0 0 0 0 0 0 0 1 dem1-0: de-emphasis filter frequency select (table 21) bst1-0: bass boost function select (table 22) dattc: dac digital attenuator control mode select 0: independent (default) 1: dependent when dattc bit is ?1?, a ttl7-0 bits control both lch and rch attenuation level, wh ile register values of attl7-0 bits are not written to a ttr7-0 bits. when dattc bit is ?0?, attl7-0 bits co ntrol lch level and attr7-0 bits control rch level. smute: soft mute control 0: normal operation (default) 1: dac outputs soft-muted addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h output select 0 moff8 hpmtn minhr rinhr dachr minhl linhl dachl default 0 0 0 0 0 0 0 0 dachl: dac lch output signal is added to lch of headphone amp. 0: off (default) 1: on linhl: input signal to lin pin is added to lch of headphone amp. 0: off (default) 1: on minhl: input signal to min pin is added to lch of headphone amp. 0: off (default) 1: on dachr: dac rch output signal is added to rch of headphone amp. 0: off (default) 1: on rinhr: input signal to rin pin is added to rch of headphone amp. 0: off (default) 1: on minhr: input signal to min pin is added to rch of headphone amp. 0: off (default) 1: on hpmtn: mute of headphone amp. 0: mute (default) 1: normal operation. moff8: soft transition for changing of dachl, linhl, minhl, dachr, rinhr, minhr and hpmtn bits 0: enable (default) 1: disable
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 46 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 09h output select 1 moff9 lom minr dacr minl rinr linl dacl default 0 0 0 0 0 0 0 0 dacl: dac lch output signal is added to buffer amp of lout. 0: off (default) 1: on linl: input signal to lin pin is added to buffer amp of lout. 0: off (default) 1: on rinr: input signal to rin pin is added to buffer amp of rout. 0: off (default) 1: on minl: input signal to min pin is added to buffer amp of lout. 0: off (default) 1: on dacr: dac rch output signal is added to buffer amp of rout. 0: off (default) 1: on minr: input signal to min pin is added to buffer amp of rout. 0: off (default) 1: on lom: lineout mono output (table 31,table 32) moff9: soft transition for changing of dacl, linl, rinr, minl, dacr and minr bits 0: enable (default) 1: disable addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah dac lch att attl7 attl6 a ttl5 attl4 attl3 attl2 attl1 attl0 0bh dac rch att attr7 attr6 attr5 attr4 attr3 attr2 attr1 attr0 default 0 0 0 0 0 0 0 0 attl7-0: setting of the at tenuation value of output si gnal from dacl (table 19) attr7-0: setting of the attenuation value of output signal from dacr (table 19) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ch lineout att 0 0 0 lmute atts3 atts2 atts1 atts0 default 0 0 0 1 0 0 0 0 atts3-0: analog volume control for lout/rout (table 30) lmute: mute control for lout/rout 0: normal operation. atts3-0 bits control attenuation value. 1: mute. atts3-0 bits are ignored. (default)
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 47 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0dh test 1 test7 test6 test5 test4 test3 test2 test1 test0 0eh test 2 test7 test6 test5 test4 test3 test2 test1 test0 0fh test 3 test7 test6 test5 test4 test3 test2 test1 test0 10h test 4 test7 test6 test5 test4 test3 test2 test1 test0 default 0 0 0 0 0 0 0 0 test7-0: test bits, ?0?data must be written. addr register name d7 d6 d5 d4 d3 d2 d1 d0 11h alc2 mode control 1 0 0 refp5 refp4 refp3 refp2 refp1 refp0 default 0 0 1 1 1 1 0 0 refp7-0: reference value at alc2 recovery operation (table 28) addr register name d7 d6 d5 d4 d3 d2 d1 d0 12h alc2 mode control 2 hpg ling alc2 wtmp1 wtmp0 lmatp1 lmatp0 rgainp default 0 0 0 0 0 0 0 0 rgainp: alc2 recovery gain step (table 27) lmatp1-0: alc2 limiter att step (table 24) wtmp1-0: alc2 recovery operation period (table 26) alc2: alc2 enable 0: alc2 disable (default) 1: alc2 enable ling: lin/rin hpl/hpr path gain 0: 0db (default) 1: ? 12db hpg: hp-amp output gain 0: 0db (default) 1: +5.5db
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 48 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 13h mode control 2 0 0 0 lmthp ltmp1 ltmp0 sdod loop default 0 0 0 0 0 0 0 0 loop: internal loopback (table 18) 0: off (default) 1: on sdod: sdto output disable (table 17) 0: enable (default) 1: disable ltmp1-0: alc2 limiter operation period (table 25) lmthp: alc2 limiter de tection level (table 23) addr register name d7 d6 d5 d4 d3 d2 d1 d0 14h mode control 3 pts1 pts0 put1 put0 fs3 fs2 fs1 fs0 default 0 0 0 0 0 0 0 0 fs3-0: sampling frequency setting (table 1) put1-0: hp-amp power-up/down time (table 38) pts1-0: hp-amp mute on/off, path on/off and alc2 recovery transition time (table 39)
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 49 - system design figure 27 shows the system connection diagram. an evaluation board [akd4665a] is available which demonstrates the optimum layout, power supply arrangements and measurement results. a vss a vdd vcom vref pdn csn cclk cdti micin mpwr a inl1 a inr1 lin rin min lout lrck mclk bick sdti sdto tvdd dvss dvdd rout hpr hpl nvss hvss hvdd cn cp a k4665aen top view 25 26 27 28 29 30 31 32 24 23 22 1 16 15 14 13 12 11 10 9 21 20 19 18 17 2 3 4 5 6 7 8 power supply 2.6 3.6v 0.1u dsp p analog ground digital ground 2.2 k 2.2u headphone 0.1u 2.2u 0.1u power supply 1.6 3.6v 10u 2.2u + + ( + ) :note ( + ) :note 10 0.1u mono mic in stereo line in external analog in stereo line out 4.7u + 0.1u + 2 figure 27. typical connection diagram note: - a 2 ? resistor must be added in series between hvdd pin and power supply line in order to limit the current. - these capacitors at cp/cn pins and hvss/nvss pins require low esr (equivalent series resistance) over all temperature range. when these capacitors are not bipolar, the positive side should be connected to cp pin and hvss respectively. - avss, dvss and hvss of the ak4665a should be distributed separately from the ground of external controllers. - all digital input should not be left floating.
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 50 - 1. grounding and power supply decoupling the ak4665a requires careful attention to power supply and grounding arrangements. avdd is usually supplied from the analog power supply in the system and dvdd&tvdd is supplied from avdd via a 10 ? resistor. alternatively if avdd, dvdd, tvdd and hvdd are supplied separately, the power up sequence is not critical. avss, dvss and hvss must be connected to the analog ground plane. system analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as close to the ak4665a as possible, with the small value ceramic capacitors being the nearest. 2. internal voltage reference internal voltage reference is output on the vref pin (typ. 2.1v). an electrolytic capacitor 4.7 f in parallel with a 0.1 f ceramic capacitor is attached between vref and avss to eliminate the effects of high frequency noise. vcom is 1.2v(typ) and is a signal ground of this chip. a 2.2 f electrolytic capacitor in parallel with a 0.1 f ceramic capacitor should be connected between vcom and avss to eliminate the effects of high frequency noise. a ceramic capacitor should be connected to vcom pin and located as close as possible to the ak4665a. no load current may be drawn from vref and vcom pins. all signals, especially clocks, should be kept away from the vcom and vref pins in order to avoid unwanted coupling into the ak4665a. 3. analog inputs the analog inputs are single-ended and the input resistance 60k ? (typ) for ainl1/ainr1 pins and 60k ? (typ)@0db/ ? 6db or 30k ? (typ)@+6db/+30db for micin pin. the input signal range is 1.5vpp (typ) centered on vcom voltage. usually, the input signal cuts dc with a capacitor. the cut-off frequency is fc=(1/2 rc). the ak4665a can accept input voltages from avss to avdd. the adc output data format is 2?s complement. the adc?s dc offset is removed by the internal hpf (fc=3.4hz@fs=44.1khz). 4. analog outputs the analog outputs are single-ended outputs. the output signal range of lineout is 1.5vpp(typ) centered on the vcom voltage. the output signal range of headphone is 1.5vpp(typ)@hpg bit = ?0? or 2.83vpp(typ)@hpg bit = ?1? centered on avss voltage. the input data format is 2?s compliment. the output voltage is a positive full scale for 7ffffh(@20bit) and negative full scale for 80000h(@20bit). the ideal output is vcom voltage (lineout) or avss voltage (headphone) for 00000h(@20bit). dc offsets on the lineout outputs is eliminated by ac coupling since the lineout outputs have a dc offset equal to vcom plus a few mv.
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 51 - package 32pin qfn (unit: mm) 4.75 0.10 5.00 0.10 4.75 0.10 0.50 0.23 24 17 25 1 16 1 0.01 0.08 32 8 9 c0.42 32 +0.07 -0.05 0.40 0.10 0.20 + 0.04 - 0.01 c exposed pad 3.5 5.00 0.10 0.85 0.05 c b a 0.10 m ab 3.5 note: the exposed pad on the bottom surface of package must be open or connected to ground. ? package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder (pb free) plate
asahi kasei [ak4665a] ms0440-e-01 2006/05 - 52 - marking 4665a x xxxx 1 xxxxx : date code identifier (5 digits) revision history date (yy/mm/dd) revision reason page contents 05/11/22 00 first edition 06/05/11 01 spec change 1,13,14 mclk=256fs/384fs/512fs ? 256fs/512fs 49 system design 2 ? series resistor was added at hvdd pin. important notice ? these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. ? akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: a. a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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